The present invention relates to an insulated gate field-effect transistor having an extension portion in each of two source/drain regions through which a current is supplied to a region of a semiconductor substrate which faces a gate electrode through a gate insulating film and which has a channel formed therein, and a method of manufacturing the same.
With respect to the scaling of an insulated gate field-effect transistor (hereinafter referred to as “a MIS transistor”), in the International Technology Roadmap for Semiconductors (ITRS), a transistor gate length Lg of a technology node hp32 is expected to become equal to or shorter than 20 nm.
In order to realize such a fine MIS transistor, it is necessary to perform the scaling of an effective oxide thickness (EOT) of an oxide film becoming a gate insulating film, and a junction depth Xj of a source/drain region concurrently with the scaling of the gate length Lg. The scaling of the EOT of the oxide film is required to ensure a drain current Ids for determining a transistor driving ability. In addition, the scaling of the junction depth Xj of the source/drain region is required to suppress the Short Channel Effect (SCE). In order to suppress the short channel effect, in particular, an electric field at a drain end needs to be relaxed. In order to attain this, there is provided a shallow junction region, referred to as the so-called Lightly Doped Drain (LDD) or an Extension, which extends from a heavily doped source/drain region to a channel side.
Normally, the extension portion of the MIS transistor is formed by implanting ions into a semiconductor substrate (or a well) in which the channel is to be formed.
However, the ion implantation technique and activation anneal technique for forming a very shallow junction which is applicable to the above-mentioned fine MIS transistor are not yet established. In addition, even if the very shallow junction can be formed by utilizing the ion implantation method, owing to its thinness, its resistance value becomes large and a series resistance value of the source and the drain increases to reduce the driving ability of the MIS transistor. Moreover, a portion, of the extension portion connected to the channel, which a gate electrode overlaps each other has a small resistance value since the carriers are accumulated therein. However, a region of the extension portion other than that portion is easy to have a large resistance value due to exhaustion of the carriers in a depletion layer. In order to prevent such a situation, the concentration of the extension portion must be increased, or the extension portion must be deeply formed. However, this is inconsistent with the suppression of the short channel effect.
A Groove Gate transistor has been proposed as the transistor having a structure adapted to solve this contradiction (refer to Non-patent document 1: Nishimatsu, et al.: Groove Gate MOSFET, 8th Conf. On Solid State Device, pp. 179 to 183, 1976).
The basic concept of this transistor structure is to make that a formation surface of a source/drain region is caused to be located upward with respect to a substrate surface having a channel formed therein to reduce an effective junction depth with respect to the channel of the source/drain region, and that the source/drain region is deeply formed to reduce its resistance value compatible with each other.
A MIS transistor in which an epitaxial growth layer is grown in substrate regions on both sides of a gate instead of forming a groove in a portion of the substrate on which a gate is to be formed, and a source/drain region is formed on the epitaxial growth layer is known as one to which that basic concept is applied (refer to, for example, Patent document 1: Japanese Patent Laid-open No. 2000-82813 (a first embodiment mode and FIG. 9)). Such a source/drain structure is called a raised (or elevated) source/drain (S/D).
According to the description of Patent document 1, a first source/drain region is formed in an inclined end portion of an epitaxial growth layer, and a second source/drain region deeper than the first source/drain region is formed in a portion of the epitaxial growth layer which is at a distance from a gate. The first source/drain region is considered to correspond to the so-called extension portion.
On the other hand, a MIS transistor is known in which an extension portion is formed from an eptaxial growth layer grown on a substrate surface, and ions are implanted from a position above the extension portion into a portion of the extension portion which is at a distance from a gate end and a substrate surface portion below that portion, thereby forming a source/drain region (refer to, for example, Non-patent document 2: Uchino, et al.: A Raised Source/Drain Technology Using In-situ P-doped SiGe and B-doped Si for 0.1 μm CMOS ULSIs, IEDM 1997, pp. 479 to 482 (1977)).
In the technique described in Patent document 1, after the epitaxial growth layer is formed, the insulating film is formed on the whole surface including the inclined end portions of the epitaxial growth layer. Thereafter, the first source/drain region and the second source/drain region are simultaneously formed by using the ion implantation method. While not described especially in Patent document 1, in this case, the ion implantation is easy to block as the gate is further approached by the insulating film portion which is formed on the inclined end portions and on sidewalls of the gate. It is estimated from this that when the second source/drain region is formed, the first source/drain region (corresponding to the extension portion) which is relatively shallower than the second source/drain region is formed so as to accompany the second source/drain region.
However, in the case of the formation of the extension portion utilizing the thickness of the insulating film through which the implanted ions penetrate, when the inclination or the like of the inclined end surface of the epitaxial growth layer contacting the insulating film changes, the configuration of the extension portion necessarily changes. This is unstable. In addition, since no ions are implanted into a portion of the gate sidewall under the insulating film, no impurities are introduced thereinto. Hence, there is encountered a problem that a space is defined between the extension portion (the first source/drain region) and the channel layer and thus this space portion has a large resistance value in some cases. In order to avoid this problem, it is required to sufficiently perform the anneal to thermally diffuse the implanted impurities, or to partially stack the gate electrode on the inclined end portion of the epitaxial growth layer. Thus, Patent document 1 discloses the technique for precisely stacking the gate electrode on the inclined end portion.
However, in the case of the technique disclosed in Patent document 1, though the stacking width between the inclined end portion and the gate electrode becomes nearly constant, there is the possibility that the extension portion disperses in position with respect to the inclined end portion. This results in that the stacking width between the extension portion and the gate electrode is easy to disperse. In addition, since the ion implantation method is used, there is also the possibility that the implanted impurities are excessively thermally diffused by the activation anneal, and the stacking width becomes larger than is needed. For this reason, in the case of the technique disclosed in Patent Document 1, the short channel effect increases, and thus it is impossible to effectively prevent the transistor characteristics from being reduced.
In addition, in the case of Patent Document 1, since the extension portion is formed by implanting the ions into the epitaxial growth layer, a steep PN junction is not obtained and the depletion layer is easy to spread. In other words, the impurity concentration distribution obtained by utilizing the ion implantation method has a concentration peak in the vicinity of the surface or in a portion which is deep from the surface side. However, the depletion layer is easy to spread since a tail portion of the impurity distribution lies in the vicinity of the PN junction, and the concentration decreases in the tail portion. For this reason, owing to the depletion layer, the exhaustion of the carriers is caused in a portion, connected to the channel, of the extension portion formed by utilizing the ion implantation method. Thus, this portion is easy to have the high resistance value.
On the other hand, in the case of the technique disclosed in Non-patent document 2, the extension portion is formed by utilizing the epitaxial growth method. Since the epitaxial growth layer is normally thin, in order to prevent the junction leakage current due to formation of a silicide layer, it is required that when the source/drain region is formed, the ion implantation energy is increased and the impurities are deeply introduced into the substrate. For this reason, in order to sufficiently increase the activation rate of the impurities, the activation anneal method needs to be performed at a high temperature. As a result, there is encountered a problem that the impurities thermally diffuse from the extension portion into the substrate at that time, and the effective junction depth Xj of the extension portion with respect to the substrate surface having the channel formed therein becomes deeper in that portion than is needed.